The present invention relates to a method of designing a semiconductor integrated circuit in which fault detection can be efficiently effected through scan-in and scan-out.
For a scan test for detecting a fault in a semiconductor integrated circuit, the semiconductor integrated circuit is required to be designed so that scan registers, that is, memory elements having a scan test function, are connected with one another to form a scan chain, and the scan chain functions as a shift register in a scan test mode.
In connecting two scan registers for forming a scan chain through the connection of the scan registers, when the scan register at the front stage has two output terminals for positive logic and negative logic, the scan registers are conventionally connected, for example, as follows: The positive logic output terminal alone of the scan register at the front stage is always connected with the scan data input terminal of the scan register at the rear stage; or alternatively, the negative logic output terminal alone of the scan register at the front stage is always connected with the scan data input terminal of the scan register at the rear stage.
Furthermore, as another conventional connection method, when one of the positive and negative logic output terminals of the scan register at the front stage is unconnected, the unconnected output terminal is used for the connection with the scan data input terminal of the scan register at the rear stage. When the two output terminals are both connected with other elements, the positive logic output terminal or the negative logic output terminal is always connected with the scan data input terminal of the scan register at the rear stage.
Now, a conventional method of designing a semiconductor integrated circuit will be described with reference to the accompanying drawings.
FIG. 20 is a circuit diagram of a scan register. In FIG. 20, a reference numeral 10 denotes a scan register for fault detection by the scanning method, a reference numeral 11 denotes a data input terminal for receiving a data in a normal operation mode, a reference numeral 12 denotes a scan data input terminal for receiving a scan data in a scan operation mode, a reference numeral 13 denotes a clock input terminal for synchronizing the scan register 10, a reference numeral 14 denotes an input switch terminal for switching between the normal operation mode and the scan operation mode, a reference numeral 15 denotes a positive logic output terminal for outputting a data having the same value as a data received at the data input terminal 11 or the scan data input terminal 12, and a reference numeral 16 denotes a negative logic output terminal for outputting a data having a value obtained by inverting a data received at the data input terminal 11 or the scan data input terminal 12. When “0” or “1” is input through the input terminal 14, the scan register 10 outputs the data received at the data input terminal 11 and the scan data input terminal 12 through the positive logic output terminal 15 synchronously with a clock signal, and simultaneously outputs, through the negative logic output terminal 16, an inverted signal of the signal output through the positive logic output terminal 15.
In the scan register 10 shown in each drawing herein referred to, the scan data input terminal 12 is indicated as SI, the positive logic output terminal 15 is indicated as Q, and the negative logic output terminal 16 is indicated as NQ for convenience, and the scan data input terminal SI, the positive logic output terminal Q and the negative logic output terminal NQ alone are shown in the drawing.
FIG. 25 is a flow chart for showing interconnecting procedures in the conventional method of designing a semiconductor integrated circuit. In the flow chart of FIG. 25, in step SZ1, connecting order of scan registers is specified; in step SZ2, a pair of scan registers adjacent to each other in the scan chain is selected; in step SZ3, it is discriminated whether or not any of the scan registers has an unconnected output terminal; in step SZ4, a positive logic output terminal is selected when there is no unconnected output terminal; in step SZ5, the unconnected output terminal is selected when there is an unconnected output terminal; in step SZ6, the selected output terminal is connected with the scan data input terminal of a scan register at the rear stage; and in step SZ7, it is discriminated whether or not all the pairs in the scan chain have been processed.
FIG. 21 is a circuit diagram of a semiconductor integrated circuit before connecting scan registers. In FIG. 21, a reference numeral 20B denotes an area for forming the semiconductor integrated circuit before the formation of a scan chain, reference numerals 21 through 25 denote scan registers working as shift registers during the scan test, reference numerals 26 through 32 denote AND gates for outputting “1” merely when two input signals are both “1”, reference numerals 33 through 35 are inverters each for outputting an inverted signal of an input signal, a reference numeral 36 denotes a scan-in terminal for receiving a signal for the scan test, and a reference numeral 37 denotes a scan-out terminal for outputting the signal for the scan test. The negative logic output terminal NQ of the scan register 22 and the positive logic output terminal Q of the scan register 25 are not used in the normal operation mode and are unconnected.
FIG. 26 is a circuit diagram obtained by conducting the allocating and interconnecting procedures of FIG. 25 on the semiconductor integrated circuit of FIG. 21. In FIG. 26, a reference numeral 20A denotes an area for allocating the semiconductor integrated circuit after the formation of the scan chain, wherein the positions and the dimensions of respective elements and wires reflect those of actual hardware. Reference numerals 21 through 37 are used to refer to the same composing elements shown in FIG. 21 and the description is omitted. A reference numeral 41Z denotes a wire for connecting the scan register 21 and the scan register 22, a reference numeral 42Z denotes a wire for connecting the scan register 22 and the scan register 23, a reference numeral 43Z denotes a wire for connecting the scan register 23 and the scan register 24, a reference numeral 44Z denotes a wire for connecting the scan register 24 and the scan register 25, and a reference numeral 45Z denotes a wire for connecting the scan register 25 and the scan-out terminal 37.
Now, specific procedures for connecting the respective scan registers by conducting the respective steps of FIG. 25 on the semiconductor integrated circuit before the formation of the scan chain shown in FIG. 21 will be described. First, in step SZ1, it is specified that the scan registers are connected in the order of the scan register 21, the scan register 22, the scan register 23, the scan register 24, the scan register 25 and the scan-out terminal 37.
Next, in step SZ2, the scan register 21 and the scan register 22 are selected as a first pair.
Then, in step SZ3, it is discriminated whether or not the positive logic output terminal Q or the negative logic output terminal NQ of the scan register 21 is unconnected. In this case, there is no unconnected terminal, and hence, the procedure proceeds to step SZ4.
Next, in step SZ4, the positive logic output terminal Q is selected, and in subsequent step SZ6, the selected positive output terminal Q is connected with the scan data input terminal SI of the scan register 22 through the wire 41Z.
Then, in step SZ7, since there remain other pairs of the scan registers, the procedure returns to step SZ2.
Subsequently, in step SZ2, the scan register 22 and the scan register 23 are selected as a next pair. In step SZ3, the negative logic output terminal NQ of the scan register 22 is discriminated to be unconnected, and hence, the procedure proceeds to step SZ5, where the negative logic output terminal NQ is selected.
Then, in step SZ6, the selected negative logic output terminal NQ is connected with the scan data input terminal SI of the scan register 23 through the wire 42Z.
The similar procedures are conducted on the remaining pairs of the scan registers, so that the positive logic output terminal Q of the scan register 23 is connected with the scan data input terminal SI of the scan register 24 through the wire 43Z, that the positive logic output terminal Q of the scan register 24 is connected with the scan data input terminal SI of the scan register 25 through the wire 44Z, and that the positive logic output terminal Q of the scan register 25 is connected with the scan data input terminal SI of the scan-out terminal 37 through the wire 45Z. Thus, the formation of the scan chain is completed.
The conventional method of designing a semiconductor integrated circuit, however, has the following problems: For example, the negative logic output terminal NQ of the scan register 22 shown in FIG. 26 is connected with the scan data input terminal SI of the scan register 23 through the wire 42z. However, a beeline distance between the negative logic output terminal NQ of the scan register 22 and the scan data input terminal SI of the scan register 23 is larger than a beeline distance between the positive logic output terminal Q of the scan register 22 and the scan data input terminal SI of the scan register 23. Therefore, the wire 42Z is elongated as compared with the case for connecting the positive logic output terminal Q of the scan register 22 with the scan data input terminal SI of the scan register 23. Thus, the length of the wire is disadvantageously increased.
Furthermore, the positive logic output terminal Q of the scan register 24 is connected with a larger number of elements than the negative logic output terminal NQ thereof. However, the scan registers 24 and 25 are connected via the positive logic output terminal Q of the scan register 24 uniformly without taking fan-out into consideration. Therefore, a larger load is applied to the positive logic output terminal Q. This results in a problem that delay of a signal from the positive logic output terminal Q of the scan register 24 to the other elements is largely increased in the normal operation mode.
Moreover, for example, in the case where a design margin corresponding to a difference between one cycle time of a clock signal at the positive logic output terminal Q of the scan register 24 and propagation time of a signal from the output terminal of the scan register 24 to the scan data input terminal SI of the scan register 25 is very small, the design margin of the positive logic output terminal Q is further decreased by connecting the positive logic output terminal Q with the scan register 25. This can result in a timing problem that the propagation of the signal cannot be finished within one clock.
Additionally, the conventional method of designing a semiconductor integrated circuit has still another problem that malfunction is caused when there is fluctuation (i.e., time skew) in time of a clock signal arriving at the clock input terminals of the respective scan registers. This problem will now be described with reference to FIGS. 26 through 28.
In FIG. 26, it is assumed that a macrocell A is used as the scan register 22 and macrocells B are used as the scan registers 23 and 24. Each of the macrocells A and B is logically identical to a scan register shown in FIG. 20. In the macrocell A, delay time required of signals entering the SI terminal to reach the Q terminal and the NQ terminal are 3 ns and 1 ns, respectively. In the macrocell B, delay time required of signals entering the SI terminal to reach the Q terminal and the NQ terminal are 1 ns and 3 ns, respectively. Description will be herein made assuming that each wire has no delay time for convenience.
FIGS. 27 and 28 are timing charts for showing the change of signals at the respective terminals of the scan registers 22, 23 and 24 in the circuit diagram of FIG. 26 obtained by the conventional method of designing a semiconductor integrated circuit. In these charts, the change of a signal at the scan data input terminal SI of the scan register 22 is shown as 22.SI, the change of signals at the clock input terminals of the scan registers 22, 23 and 24 are shown as 22.CK, 23.CK and 24.CK, respectively, the change of signals at the negative logic output terminals NQ of the scan registers 22, 23 and 24 are shown as 22.NQ, 23.NQ and 24.NQ, respectively, and the change of signals at the positive logic output terminals Q of the scan registers 22, 23 and 24 are shown as 22.Q, 23.Q and 24.Q, respectively.
FIG. 27 is an ideal timing chart where there is no fluctuation in the time of a clock signal reaching at the clock input terminals of the scan registers 22 through 24. It is assumed that data of 1, 0 and 1 in this order are input to the scan data input terminal SI of the scan register 22 from the positive logic output terminal Q of the scan data 21 at the previous stage synchronously with the clock signal. Each of the negative logic output terminal NQ of the scan register 22 and the positive logic output terminals Q of the scan registers 23 and 24 outputs a data, fetched 1 ns after the input of the clock signal, to the scan data input terminal SI of the scan register at the subsequent stage. Accordingly, the input data is shifted by the scan registers 22, 23 and 24 in accordance with the clock signal, so that the signals at the negative logic output terminal NQ of the scan register 22 and the positive logic output terminals Q of the scan registers 23 and 24 attain values of 0, 1 and 0, respectively after three cycles of the clock signal.
FIG. 28 is a timing chart where the time of the clock signal reaching the scan register 23 is delayed by 2 ns as compared with that reaching the scan registers 22 and 24. In this case, since the clock signal of the scan register 23 is input ins later than the change of the signal input to the scan data input terminal SI of the scan register 23, a new signal obtained immediately after the change at the scan data input terminal SI of the scan register 23, i.e., a signal subsequent to a signal inherently to be fetched, is fetched. Accordingly, the signals at the negative logic output terminal NQ of the scan register 22 and the positive logic output terminals Q of the scan registers 23 and 24 attain values of 0, 0 and 1, respectively after three cycles of the clock signal. Thus, the signal values are different from the expected values obtained in the ideal timing chart of FIG. 27, and hence, malfunction can be caused.